Standard cell application-specific integrated circuits (ASICs) provide a number of significant advantages over other types of integrated circuits, including more manageable die size, lower piece-part cost, higher performance, and more reliable design flow. The standard cell approach is generally preferred to other competing approaches such as custom design and programmable logic. Yet, this approach typically has high non-recurring expense (NRE) and process cycle time for development of a given integrated circuit (IC) design. The principal components of the NRE are the cost of a new lot start and the cost of a new mask set as required to implement changes in a standard cell design. As transistor technology shrinks in size, the lot start and mask set costs can increase considerably. With regard to process cycle time, ASICs typically undergo several design iterations before full production. Final production with pure standard cell technology can thus be expensive and time consuming at a time when market forces are squeezing costs and shortening development cycles.
One technique for reducing the NRE and process cycle time involves the embedding of spare standard cell gates in a chip netlist to be used at a later time for design changes or to fix inevitable bugs. These spare cells typically include some kind of NAND and NOR gates as well as multiplexers, inverters, and flip-flops that are hopefully useful for design changes and debugging. Traditionally, the spare cells are distributed across an IC in a limited manner (e.g., one spare gate for every 100 flip-flops). Wiring changes and debugging using spare cells can be difficult due to poor spare cell placement, because the spare cells may not be close to the point where their spare logic is needed.
Another way to debug an IC is through the use of a scan chains. Scan chain chains are widely used to efficiently test the logic of different designs on a chip. An effective scan chain test can detect a high percentage of manufacturing failures and greatly reduce the amount time and data necessary to ensure a particular chip design is working properly. Scan chains typically operate in two modes: (1) a scan shift mode; and (2) a capture, or functional, mode. In the scan shift mode, a test value is shifted into serially connected flip-flops of the scan chain. In capture mode, the flip-flops are allowed to function properly by passing data to combinational logic of a design under test (DUT) and receiving signals from the DUT as inputs to the next sequential flip-flop in the scan chain. Testing occurs by first shifting the test value into the flip-flops during scan shift mode and then supplying the test value to the DUT during capture mode to see how the DUT responds. The final flip-flop in the chain produces an output value that can be compared against what should have been produced by the DUT, and if the two do not match, the testing strongly indicates there is a flaw or bug in the DUT.
A D flip-flop has a single data input, a reset input, a clock input, and multiple flip-flop outputs. Upon detection of a particular clock action (e.g., a rising edge), a D flip-flop is designed to assign the value of the data input to a standard function output and a test output. In a scan chain using D flip-flops, the standard function output of each D flip-flop is connected to circuitry of the DUT, and the test output of each D flip-flop is connected to the test input of the next flip-flop in the chain. During capture mode, the test output of the D flip-flop does not matter while the standard function output does because the latter is supplying data values to circuitry of the DUT. Conversely, in scan shift mode, the standard function output of the D flip-flop does not matter while the test output does because the latter is being used to shift in the test value. Even though one of the two D flip-flop outputs do not matter at any given time, signals are still being sent across both outputs. Power is required to switch these unnecessary signals of the two D flip-flop outputs, and this unnecessary signal switching is wasteful for at least one flip-flop output at any given time—not only for the power required to switch the output but also for downstream electrical activity in the IC that may be affected by the unnecessary output.